1. Field of the Invention
The present invention relates to a semiconductor memory chip, and more particularly to a memory chip having a multiple inputs/output system.
2. Description of the Conventional Art
Generally, a conventional multiple input/output memory chip is fabricated by dividing a memory cell into unit blocks, each being capable of inputting/outputting 8-bit data. Also, the conventional multiple input/output memory chip is used by expanding an entire memory to a memory having an 8, 16 or 32-bit input/output by enabling one unit block or a plurality of unit blocks in accordance with a predetermined signal.
FIG. 1 illustrates an example of the conventional multiple input/output memory chip using .times.8 or .times.16 bit which has a 32K or 64K memory capacity.
As shown therein, there are mainly a first memory block BLOCK1 which simultaneously inputs/outputs 8-bit data by decoding an address signal in accordance with a first block selection signal BLK1 and thus enabling a corresponding memory cell and a second memory block BLOCK2 which simultaneously inputs and outputs 8-bit data by decoding an address signal in accordance with a second block selection signal BLK2 and thus enabling a corresponding memory cell.
In such way, one memory chip is divided into two unit blocks which enable the input/output of the 8-bit data. Then, when using .times.8 bit, only the first block BLOCK1 operates by activating the first block selection signal BLK1, while when using .times.16 bit, both of the first and second blocks BLOCK1, BLOCK2 operate by activating the first and second block selection signals BLK1, BLK2. Accordingly, it is possible to use one memory chip as memories of 4K.times.8 size and 4K.times.16 size, thus considerably reducing the costs for separately fabricating memory chips.
More particularly, the first memory block BLOCK1 includes a first memory cell array 10 consisting of 512 word lines (rows) and 64 bit lines (columns), a first row decoder 11 for decoding a 9-bit row address signal XADDR in accordance with a first block selection signal BLK1, a first word line driving unit 12 for driving a word line among the 512 word lines in accordance with the decoded address signal, a first column selecting unit 13 for selecting 8 among the 64 bit lines of the first memory cell array 10 in accordance with a 3-bit column address signal YADDR, a first sense amp unit 14 for amplifying the data of the 8 memory cells which have been selected by the first word line driving unit 12 and the first column selecting unit 13 to a predetermined size, a first sense amp driving unit 15 for driving the first sense amp unit 14 in accordance with the first block selection signal BLK1 and a first data input/output unit 16 for input/outputting 8-bit data through a data bus DB1.
The second memory block BLOCK2 which has the same configuration with the first memory block BLOCK1 includes a second memory cell array 10', a second row decoder 11', a second word line driving unit 12', a second column selecting unit 13', a second sense amp unit 14', a second sense amp driving unit 15' and a second data input/output unit 16. Here, each of the first and second column selecting unit 13, 13' consists of 8 column selects (C/S), 8 columns per each C/S, and each of the first and second sense amp units 14, 14' includes 8 sense amps, through which 8-bit data may be simultaneously inputted/outputted.
When such multiple input/output memory chip has the input/output (I/O) system using .times.8 bit, only the first memory block BLOCK1 operates by activating the first block selecting signal BLK1 and disabling the second block selecting signal BLK2. The row decoder 11 which received the first block selection signal BLK1 is enabled and thus decodes and outputs the inputted 9-bit row address signal XADDR. Then, the first word line driving unit 12 which received the address signal decoded by the first row decoder 11 drives a corresponding word line among the 512 word lines of the first memory cell array 10, and in accordance with the 3-bit column address YADDR the 8 C/Ss of the first column selection unit 13 respectively select each bit line among 8 bit lines connected with each C/S, thus total selecting 8 memory cells.
While, the first sense amp driving unit 15 enabled by receiving the first block selection signal BLK1 drives 8 sense amps of the first sense amp unit 14, for thereby amplifying data stored in the selected 8 memory cells and outputting the data through the data bus DB1 or storing the data in the memory cells. Then, the first data input/output unit 16 externally outputs the data which have applied through the data bus DB1. Such process implements the 4K.times.8 memory by operating only the first memory block BLOCK1, and both of the first and second block selection signals BLK1, BLK2 are activated for using the conventional multiple input/output memory chip as the 4K.times.16 memory. Then, the first memory block BLOCK1 operates the same as the above-described 4K.times.8 memory and also the second memory block BLOCK2 has the same operation as in the first block BLOCK1.
In other words, if the second row decoder 11' which received the second block selection signal BLK2 decodes and outputs an enabled 9-bit row address signal XADDR, the second word line driving unit 12' which received the decoded address signal drives one corresponding word line among the 512 word lines of the second memory cell array 10', and in accordance with the 3-bit column address YADDR the 8 C/Ss in the second column selection unit 13' select each bit line of the 8 columns connected with each C/S, thus selecting 8 memory cells.
The second sense amp driving unit 15' which received the second block selection signal BLK2 is enabled and drives the 8 sense amps of the second sense amp unit 14' for thereby amplifying the data stored in the selected 8 memory cells and loading the resultant data into the data bus DB2. Thus, the second data input/output unit 16' externally outputs the 8-bit data loaded in the data bus DB2.
In the above-described process, 8-bit data are inputted/outputted in the first and second memory blocks BLOCK1, BLOCK2, respectively and thus it is possible for 16-bit data to be simultaneously inputted/outputted.
However, since the two memory blocks BLOCK1, BLOCK2 should be simultaneously enabled at all times in order to use the memory circuit having the conventional multiple input/output system as the memory using .times.16 bit, the operation current of the cell twice multiplies, thus making an unstable condition of the whole memory. In addition, it is required to inconveniently connect the couple of the memory chips to use the memory circuit as the memory using .times.32 bit.